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synced 2026-07-17 07:20:34 +08:00
boards: new px4_fmu-v6c board support (#19544)
This commit is contained in:
committed by
Daniel Agar
parent
8e789bcc7f
commit
21567ca187
@@ -92,7 +92,13 @@ enum Timer {
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Timer13,
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Timer14,
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#ifdef STM32_TIM15_BASE
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Timer15
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Timer15,
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#endif
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#ifdef STM32_TIM16_BASE
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Timer16,
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#endif
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#ifdef STM32_TIM17_BASE
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Timer17
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#endif
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};
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enum Channel {
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@@ -161,6 +167,16 @@ static inline constexpr uint32_t timerBaseRegister(Timer::Timer timer)
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case Timer::Timer15: return STM32_TIM15_BASE;
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#endif
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#ifdef STM32_TIM16_BASE
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case Timer::Timer16: return STM32_TIM16_BASE;
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#endif
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#ifdef STM32_TIM17_BASE
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case Timer::Timer17: return STM32_TIM17_BASE;
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#endif
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default: break;
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}
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@@ -86,6 +86,8 @@ static inline constexpr uint32_t getTimerUpdateDMAMap(Timer::Timer timer, const
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case Timer::Timer13:
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case Timer::Timer14:
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case Timer::Timer15:
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case Timer::Timer16:
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case Timer::Timer17:
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break;
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}
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@@ -49,6 +49,8 @@ static inline constexpr timer_io_channels_t initIOTimerGPIOInOut(Timer::TimerCha
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switch (timer.timer) {
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case Timer::Timer1:
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case Timer::Timer2:
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case Timer::Timer16:
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case Timer::Timer17:
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gpio_af = GPIO_AF1;
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break;
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@@ -274,6 +276,28 @@ static inline constexpr io_timers_t initIOTimer(Timer::Timer timer, DMA dshot_dm
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ret.vectorno = STM32_IRQ_TIM15;
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#ifdef CONFIG_STM32_TIM15
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nuttx_config_timer_enabled = true;
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#endif
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break;
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case Timer::Timer16:
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ret.base = STM32_TIM16_BASE;
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ret.clock_register = STM32_RCC_APB2ENR;
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ret.clock_bit = RCC_APB2ENR_TIM16EN;
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ret.clock_freq = STM32_APB2_TIM16_CLKIN;
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ret.vectorno = STM32_IRQ_TIM16;
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#ifdef CONFIG_STM32_TIM16
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nuttx_config_timer_enabled = true;
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#endif
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break;
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case Timer::Timer17:
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ret.base = STM32_TIM17_BASE;
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ret.clock_register = STM32_RCC_APB2ENR;
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ret.clock_bit = RCC_APB2ENR_TIM17EN;
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ret.clock_freq = STM32_APB2_TIM17_CLKIN;
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ret.vectorno = STM32_IRQ_TIM17;
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#ifdef CONFIG_STM32_TIM17
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nuttx_config_timer_enabled = true;
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#endif
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break;
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}
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