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synced 2026-07-21 23:30:35 +08:00
STM32 new CAN initialization
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@@ -488,10 +488,26 @@ bool CanIface::waitMsrINakBitStateChange(bool target_state)
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int CanIface::init(const uavcan::uint32_t bitrate, const OperatingMode mode)
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{
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int res = 0;
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/*
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* We need to silence the controller in the first order, otherwise it may interfere with the following operations.
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*/
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{
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CriticalSectionLocker lock;
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can_->MCR &= ~bxcan::MCR_SLEEP; // Exit sleep mode
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can_->MCR |= bxcan::MCR_INRQ; // Request init
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can_->IER = 0; // Disable interrupts while initialization is in progress
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}
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if (!waitMsrINakBitStateChange(true))
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{
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UAVCAN_STM32_LOG("MSR INAK not set");
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return -1;
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}
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/*
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* Object state
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* Object state - interrupts are disabled, so it's safe to modify it now
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*/
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rx_queue_.reset();
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error_cnt_ = 0;
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@@ -505,31 +521,17 @@ int CanIface::init(const uavcan::uint32_t bitrate, const OperatingMode mode)
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* CAN timings for this bitrate
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*/
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Timings timings;
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res = computeTimings(bitrate, timings);
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if (res < 0)
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const int timings_res = computeTimings(bitrate, timings);
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if (timings_res < 0)
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{
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goto leave;
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return timings_res;
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}
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UAVCAN_STM32_LOG("Timings: presc=%u sjw=%u bs1=%u bs2=%u",
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unsigned(timings.prescaler), unsigned(timings.sjw), unsigned(timings.bs1), unsigned(timings.bs2));
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/*
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* Hardware initialization
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* Hardware initialization (the hardware has already confirmed initialization mode, see above)
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*/
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{
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CriticalSectionLocker lock;
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can_->MCR &= ~bxcan::MCR_SLEEP; // Exit sleep mode
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can_->MCR |= bxcan::MCR_INRQ; // Request init
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}
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if (!waitMsrINakBitStateChange(true))
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{
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UAVCAN_STM32_LOG("MSR INAK not set");
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res = -1;
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goto leave;
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}
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can_->MCR = bxcan::MCR_ABOM | bxcan::MCR_AWUM | bxcan::MCR_INRQ; // RM page 648
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can_->BTR = ((timings.sjw & 3U) << 24) |
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@@ -549,8 +551,7 @@ int CanIface::init(const uavcan::uint32_t bitrate, const OperatingMode mode)
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if (!waitMsrINakBitStateChange(false))
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{
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UAVCAN_STM32_LOG("MSR INAK not cleared");
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res = -1;
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goto leave;
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return -1;
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}
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/*
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@@ -583,8 +584,7 @@ int CanIface::init(const uavcan::uint32_t bitrate, const OperatingMode mode)
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can_->FMR &= ~bxcan::FMR_FINIT;
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}
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leave:
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return res;
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return 0;
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}
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void CanIface::handleTxMailboxInterrupt(uavcan::uint8_t mailbox_index, bool txok, const uavcan::uint64_t utc_usec)
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