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synced 2026-10-20 05:53:34 +08:00
uvify_core: add board_dma_map.h and enable SPI1 DMA
- synced with px4_fmu-v4
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@@ -48,4 +48,5 @@ target_link_libraries(drivers_board
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nuttx_arch # sdio
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nuttx_drivers # sdio
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px4_layer
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arch_io_pins
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)
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@@ -284,7 +284,7 @@
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#define BOARD_HAS_PWM DIRECT_PWM_OUTPUT_CHANNELS
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/* This board provides a DMA pool and APIs. */
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#define BOARD_DMA_ALLOC_POOL_SIZE 5120
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#define BOARD_DMA_ALLOC_POOL_SIZE (5120 + 512 + 1024) // 5120 fat + 512 + 1024 spi
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#define BOARD_HAS_ON_RESET 1
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@@ -73,10 +73,12 @@
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#include <systemlib/px4_macros.h>
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#include <px4_arch/io_timer.h>
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#include <px4_platform_common/init.h>
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#include <px4_platform/board_dma_alloc.h>
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#include <drivers/drv_pwm_output.h>
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#include <px4_arch/io_timer.h>
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/****************************************************************************
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* Pre-Processor Definitions
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****************************************************************************/
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@@ -146,7 +148,7 @@ __EXPORT void board_on_reset(int status)
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px4_arch_configgpio(io_timer_channel_get_gpio_output(i));
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}
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/*
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/**
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* On resets invoked from system (not boot) insure we establish a low
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* output state (discharge the pins) on PWM pins before they become inputs.
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*/
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@@ -57,4 +57,3 @@ constexpr timer_io_channels_t timer_io_channels[MAX_TIMER_IO_CHANNELS] = {
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constexpr io_timers_channel_mapping_t io_timers_channel_mapping =
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initIOTimerChannelMapping(io_timers, timer_io_channels);
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